From 6f0df5a4b8cbd635afdcf792c61cda02001a9182 Mon Sep 17 00:00:00 2001 From: Minseong Jang Date: Sun, 27 Feb 2022 22:39:21 +0900 Subject: [PATCH] Modify comments for cargo doc --- src/asm/mod.rs | 36 ++++++++++++++++++++++++------------ src/ir/interp.rs | 3 ++- src/ir/mod.rs | 6 ++++-- src/lib.rs | 2 +- 4 files changed, 31 insertions(+), 16 deletions(-) diff --git a/src/asm/mod.rs b/src/asm/mod.rs index 3f4b25f..1ac10f5 100644 --- a/src/asm/mod.rs +++ b/src/asm/mod.rs @@ -22,14 +22,16 @@ pub struct TranslationUnit { #[derive(Debug, Clone, PartialEq, Eq)] pub struct Section { /// Section Headers provice size, offset, type, alignment and flags of the sections - /// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#section-header + /// + /// For more details: pub header: Vec, pub body: T, } /// An object file is made up of multiple sections, with each section corresponding to /// distinct types of executable code or data. -/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#sections +/// +/// For more details: impl Section { pub fn new(header: Vec, body: T) -> Self { Self { header, body } @@ -76,7 +78,8 @@ impl Block { /// The assembler implements a number of directives that control the assembly of instructions /// into an object file. -/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-directives +/// +/// For more details: #[derive(Debug, Clone, PartialEq, Eq)] pub enum Directive { /// .align integer @@ -129,7 +132,8 @@ pub enum SymbolType { #[derive(Debug, Clone, PartialEq, Eq)] pub enum Instruction { /// R-type instruction format - /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p) + /// + /// For more details: (104p) RType { instr: RType, rd: Register, @@ -137,7 +141,8 @@ pub enum Instruction { rs2: Option, }, /// I-type instruction format - /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p) + /// + /// For more details: (104p) IType { instr: IType, rd: Register, @@ -145,7 +150,8 @@ pub enum Instruction { imm: Immediate, }, /// S-type instruction format - /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p) + /// + /// For more details: (104p) SType { instr: SType, rs1: Register, @@ -153,7 +159,8 @@ pub enum Instruction { imm: Immediate, }, /// B-type instruction format - /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p) + /// + /// For more details: (104p) BType { instr: BType, rs1: Register, @@ -506,8 +513,10 @@ pub enum UType { /// The assembler implements a number of convenience psuedo-instructions that are formed from /// instructions in the base ISA, but have implicit arguments or in some case reversed arguments, /// that result in distinct semantics. -/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-pseudo-instructions -/// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (110p) +/// +/// For more details: +/// - +/// - (110p) #[derive(Debug, Clone, PartialEq, Eq)] pub enum Pseudo { /// la rd, symbol @@ -593,7 +602,8 @@ impl Immediate { /// The relocation function creates synthesize operand values that are resolved /// at program link time and are used as immediate parameters to specific instructions. -/// https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md +/// +/// For more details: #[derive(Debug, Clone, PartialEq, Eq)] pub enum RelocationFunction { /// %hi @@ -603,7 +613,8 @@ pub enum RelocationFunction { } /// `Label` is used as branch, unconditional jump targets and symbol offsets. -/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#labels +/// +/// For more details: #[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)] pub struct Label(pub String); @@ -675,7 +686,8 @@ impl DataSize { // TODO: Add calling convention information (caller/callee-save registers) /// ABI name for RISC-V integer and floating-point register -/// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (109p) +/// +/// For more details: (109p) #[derive(Debug, Clone, PartialEq, Eq, Hash, Copy)] pub enum Register { Zero, diff --git a/src/ir/interp.rs b/src/ir/interp.rs index bcdd6da..1d1bfeb 100644 --- a/src/ir/interp.rs +++ b/src/ir/interp.rs @@ -26,7 +26,8 @@ pub enum Value { /// /// * Casting from an f32 to an f64 is perfect and lossless (f32 -> f64) /// * Casting from an f64 to an f32 will produce the closest possible value (f64 -> f32) - /// https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions + /// + /// For more details: value: OrderedFloat, width: usize, }, diff --git a/src/ir/mod.rs b/src/ir/mod.rs index f79ca18..38e2d43 100644 --- a/src/ir/mod.rs +++ b/src/ir/mod.rs @@ -221,7 +221,8 @@ pub enum Instruction { target_dtype: Dtype, }, /// `GetElementPtr` is inspired from `getelementptr` instruction of LLVM. - /// https://llvm.org/docs/LangRef.html#i-getelementptr + /// + /// For more details: GetElementPtr { ptr: Operand, offset: Operand, @@ -501,7 +502,8 @@ pub enum Constant { /// /// * Casting from an f32 to an f64 is perfect and lossless (f32 -> f64) /// * Casting from an f64 to an f32 will produce the closest possible value (f64 -> f32) - /// https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions + /// + /// For more details: value: OrderedFloat, width: usize, }, diff --git a/src/lib.rs b/src/lib.rs index 0b2faae..47cceee 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -44,7 +44,7 @@ mod tests; mod utils; mod write_base; -mod asm; +pub mod asm; mod c; pub mod ir;