From 9ed3e7ca3fbd0d4b6e6bc20472b43fcbf1853cbe Mon Sep 17 00:00:00 2001 From: static Date: Mon, 16 Jun 2025 04:37:35 +0000 Subject: [PATCH] HW7 (5) --- src/asmgen/mod.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/asmgen/mod.rs b/src/asmgen/mod.rs index cd785d0..3e0d2f6 100644 --- a/src/asmgen/mod.rs +++ b/src/asmgen/mod.rs @@ -57,7 +57,7 @@ impl Asmgen { if *size != directives.len() { directives.push(asm::Directive::Zero( (size - directives.len()) - * (get_dtype_size(&inner, structs) as usize), + * (get_dtype_size(inner, structs) as usize), )); } } @@ -610,7 +610,7 @@ impl Asmgen { rid: ptr_rid, dtype: ptr_dtype, } => match ptr_rid { - ir::RegisterId::Temp { .. } => { + ir::RegisterId::Temp { .. } | ir::RegisterId::Arg { .. } => { if let Some(size) = is_struct(&value_dtype, structs) { let rs1 = get_lhs_register(ptr_dtype); self.translate_load_operand(ptr, rs1, context); @@ -1058,7 +1058,7 @@ impl Asmgen { rid: ptr_rid, dtype: ptr_dtype, } => match ptr_rid { - ir::RegisterId::Temp { .. } => { + ir::RegisterId::Temp { .. } | ir::RegisterId::Arg { .. } => { let rs1 = get_lhs_register(ptr_dtype); let rs2 = get_rhs_register(&offset_dtype); self.translate_load_operand(ptr, rs1, context); @@ -1629,7 +1629,7 @@ fn ceil_to_multiple_of_16(x: u64) -> u64 { fn get_dtype_size(dtype: &ir::Dtype, structs: &HashMap>) -> u64 { let (size, _) = dtype.size_align_of(structs).unwrap(); - return size as u64; + size as u64 } fn upgrade_dtype(dtype: &ir::Dtype) -> ir::Dtype {