mirror of
https://github.com/kmc7468/cs420.git
synced 2025-12-14 22:38:46 +00:00
HW8 (8)
This commit is contained in:
static
@@ -249,7 +249,7 @@ impl InferenceGraph {
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if !analysis.has_memcpy_in_prologue {
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for (aid, dtype) in code.blocks[&code.bid_init].phinodes.iter().enumerate() {
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let rid = ir::RegisterId::arg(code.bid_init, aid);
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if analysis.is_temporary2(&rid, &lives) {
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if analysis.is_temporary2(&rid, &lives, true) {
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if is_integer(dtype) {
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let (_, asm_reg) = vertices.get_mut(&rid).unwrap();
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*asm_reg = asm::Register::arg(
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@@ -269,7 +269,7 @@ impl InferenceGraph {
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for (bid, iid, _, reg) in &analysis.calls {
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let rid = ir::RegisterId::temp(*bid, *iid);
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if analysis.is_temporary2(&rid, &lives) {
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if analysis.is_temporary2(&rid, &lives, true) {
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if let Some(reg) = reg {
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let (_, asm_reg) = vertices.get_mut(&rid).unwrap();
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*asm_reg = *reg;
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@@ -307,6 +307,7 @@ impl InferenceGraph {
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reg,
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asm::Register::Saved(asm::RegisterType::Integer, _)
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| asm::Register::Arg(asm::RegisterType::Integer, _)
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| asm::Register::Temp(asm::RegisterType::Integer, _)
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)
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{
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return Some(*reg);
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@@ -316,6 +317,7 @@ impl InferenceGraph {
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reg,
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asm::Register::Saved(asm::RegisterType::FloatingPoint, _)
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| asm::Register::Arg(asm::RegisterType::FloatingPoint, _)
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| asm::Register::Temp(asm::RegisterType::FloatingPoint, _)
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)
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{
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return Some(*reg);
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@@ -324,6 +326,19 @@ impl InferenceGraph {
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})
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.collect::<HashSet<_>>();
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if is_integer(dtype) {
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let smallest_temp_reg = smallest_missing_integer(
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&neighbor_registers
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.iter()
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.filter_map(|reg| {
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if let asm::Register::Temp(_, i) = reg {
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Some(*i)
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} else {
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None
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}
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})
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.collect(),
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3,
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); // t0~2는 못 씀
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let smallest_arg_reg = smallest_missing_integer(
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&neighbor_registers
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.iter()
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@@ -350,7 +365,15 @@ impl InferenceGraph {
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.collect(),
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1,
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); // s0는 못 씀
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if smallest_arg_reg <= 7 && analysis.is_temporary2(&rid, &lives) {
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if smallest_temp_reg <= 6 && analysis.is_temporary2(&rid, &lives, false) {
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let _unused = vertices.insert(
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rid,
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(
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dtype.clone(),
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asm::Register::temp(asm::RegisterType::Integer, smallest_temp_reg),
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),
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);
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} else if smallest_arg_reg <= 7 && analysis.is_temporary2(&rid, &lives, true) {
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let _unused = vertices.insert(
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rid,
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(
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@@ -370,6 +393,19 @@ impl InferenceGraph {
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// Spilling
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}
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} else if is_float(dtype) {
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let smallest_temp_reg = smallest_missing_integer(
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&neighbor_registers
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.iter()
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.filter_map(|reg| {
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if let asm::Register::Temp(_, i) = reg {
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Some(*i)
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} else {
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None
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}
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})
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.collect(),
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2,
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); // ft0~1은 못 씀
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let smallest_arg_reg = smallest_missing_integer(
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&neighbor_registers
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.iter()
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@@ -396,7 +432,18 @@ impl InferenceGraph {
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.collect(),
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0,
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);
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if smallest_arg_reg <= 7 && analysis.is_temporary2(&rid, &lives) {
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if smallest_temp_reg <= 11 && analysis.is_temporary2(&rid, &lives, false) {
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let _unused = vertices.insert(
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rid,
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(
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dtype.clone(),
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asm::Register::temp(
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asm::RegisterType::FloatingPoint,
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smallest_temp_reg,
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),
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),
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);
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} else if smallest_arg_reg <= 7 && analysis.is_temporary2(&rid, &lives, true) {
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let _unused = vertices.insert(
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rid,
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(
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@@ -493,6 +540,7 @@ impl Analysis {
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&self,
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reg: &ir::RegisterId,
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lives: &HashMap<ir::RegisterId, HashSet<ir::RegisterId>>,
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is_a_reg: bool,
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) -> bool {
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for (call_bid, call_iid, call_args, _) in &self.calls {
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let lives_before = lives
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@@ -501,7 +549,8 @@ impl Analysis {
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let lives_after = lives
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.get(&ir::RegisterId::temp(*call_bid, call_iid + 1))
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.unwrap();
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if lives_before.contains(reg) && (call_args.contains(reg) || lives_after.contains(reg))
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if lives_before.contains(reg)
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&& ((is_a_reg && call_args.contains(reg)) || lives_after.contains(reg))
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{
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return false;
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}
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@@ -920,14 +969,14 @@ impl Asmgen {
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packing_size += field_size;
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} else {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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stack_offset,
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&mut insts,
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);
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insts.push(asm::Instruction::SType {
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instr: asm::SType::SD,
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(
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asm::RegisterType::Integer,
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num_int_args,
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@@ -941,14 +990,14 @@ impl Asmgen {
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} else if is_float(field_dtype) {
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if is_packing {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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stack_offset,
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&mut insts,
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);
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insts.push(asm::Instruction::SType {
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instr: asm::SType::SD,
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(
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asm::RegisterType::Integer,
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num_int_args,
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@@ -960,14 +1009,14 @@ impl Asmgen {
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}
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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stack_offset,
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&mut insts,
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);
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insts.push(asm::Instruction::SType {
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instr: asm::SType::store(field_dtype.deref().clone()),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(
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asm::RegisterType::FloatingPoint,
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num_float_args,
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@@ -982,14 +1031,14 @@ impl Asmgen {
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if is_packing {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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stack_offset,
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&mut insts,
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);
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insts.push(asm::Instruction::SType {
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instr: asm::SType::SD,
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(asm::RegisterType::Integer, num_int_args),
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imm: asm::Immediate::Value(packing_start_offset as u64),
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});
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@@ -1908,7 +1957,7 @@ impl Asmgen {
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ir::Operand::Register { rid, .. } => match rid {
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ir::RegisterId::Temp { bid, iid } => {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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context.stack_offsets[rid],
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&mut context.insts,
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@@ -1952,7 +2001,7 @@ impl Asmgen {
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asm::RegisterType::Integer,
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num_int_args,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(
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packing_start_offset as u64,
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),
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@@ -1970,7 +2019,7 @@ impl Asmgen {
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asm::RegisterType::Integer,
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num_int_args,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(
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packing_start_offset as u64,
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),
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@@ -1985,7 +2034,7 @@ impl Asmgen {
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asm::RegisterType::FloatingPoint,
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num_float_args,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(packing_start_offset as u64),
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});
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num_float_args += 1;
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@@ -2001,7 +2050,7 @@ impl Asmgen {
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asm::RegisterType::Integer,
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num_int_args,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(packing_start_offset as u64),
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});
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num_int_args += 1;
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@@ -2115,14 +2164,14 @@ impl Asmgen {
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.unwrap();
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if is_integer(field_dtype) {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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context.stack_offsets[&rid],
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&mut context.insts,
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);
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context.insts.push(asm::Instruction::SType {
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instr: asm::SType::store(field_dtype.deref().clone()),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(
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asm::RegisterType::Integer,
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num_int_fields,
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@@ -2132,14 +2181,14 @@ impl Asmgen {
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num_int_fields += 1;
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} else if is_float(field_dtype) {
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self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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context.stack_offsets[&rid],
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&mut context.insts,
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);
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context.insts.push(asm::Instruction::SType {
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instr: asm::SType::store(field_dtype.deref().clone()),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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rs2: asm::Register::arg(
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asm::RegisterType::FloatingPoint,
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num_float_fields,
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@@ -2623,7 +2672,7 @@ impl Asmgen {
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},
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ir::Operand::Register { rid, .. } => match rid {
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ir::RegisterId::Temp { bid, iid } => self.translate_addi(
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asm::Register::T5,
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asm::Register::T2,
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asm::Register::S0,
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context.stack_offsets[rid],
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&mut context.insts,
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@@ -2648,7 +2697,7 @@ impl Asmgen {
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asm::RegisterType::Integer,
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num_int_fields,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(offset as u64),
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});
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num_int_fields += 1;
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@@ -2659,7 +2708,7 @@ impl Asmgen {
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asm::RegisterType::FloatingPoint,
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num_float_fields,
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),
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rs1: asm::Register::T5,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(offset as u64),
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});
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num_float_fields += 1;
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@@ -2717,13 +2766,13 @@ impl Asmgen {
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32 => context
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.insts
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.push(asm::Instruction::Pseudo(asm::Pseudo::Li {
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rd: asm::Register::T4,
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rd: asm::Register::T2,
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imm: (*value as f32).to_bits() as u64,
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})),
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64 => context
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.insts
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.push(asm::Instruction::Pseudo(asm::Pseudo::Li {
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rd: asm::Register::T4,
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rd: asm::Register::T2,
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imm: value.to_bits(),
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})),
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_ => unreachable!(),
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@@ -2731,7 +2780,7 @@ impl Asmgen {
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context.insts.push(asm::Instruction::RType {
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instr: asm::RType::fmv_int_to_float(ir::Dtype::float(width)),
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rd,
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rs1: asm::Register::T4,
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rs1: asm::Register::T2,
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rs2: None,
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});
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}
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@@ -3101,14 +3150,14 @@ impl Asmgen {
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});
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} else {
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insts.push(asm::Instruction::Pseudo(asm::Pseudo::Li {
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rd: asm::Register::T3,
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rd: asm::Register::T2,
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imm,
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}));
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insts.push(asm::Instruction::RType {
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instr: asm::RType::add(ir::Dtype::int(64)),
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rd,
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rs1,
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rs2: Some(asm::Register::T3),
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rs2: Some(asm::Register::T2),
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});
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}
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}
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@@ -3131,18 +3180,18 @@ impl Asmgen {
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});
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} else {
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insts.push(asm::Instruction::Pseudo(asm::Pseudo::Li {
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rd: asm::Register::T3,
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rd: asm::Register::T2,
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imm,
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}));
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insts.push(asm::Instruction::RType {
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instr: asm::RType::add(ir::Dtype::int(64)),
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rd: asm::Register::T3,
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rd: asm::Register::T2,
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rs1,
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rs2: Some(asm::Register::T3),
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rs2: Some(asm::Register::T2),
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});
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insts.push(asm::Instruction::SType {
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instr,
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rs1: asm::Register::T3,
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rs1: asm::Register::T2,
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rs2,
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imm: asm::Immediate::Value(0),
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});
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@@ -3167,19 +3216,19 @@ impl Asmgen {
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});
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} else {
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insts.push(asm::Instruction::Pseudo(asm::Pseudo::Li {
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rd: asm::Register::T3,
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rd: asm::Register::T2,
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imm,
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}));
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insts.push(asm::Instruction::RType {
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instr: asm::RType::add(ir::Dtype::int(64)),
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rd: asm::Register::T3,
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rd: asm::Register::T2,
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rs1,
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rs2: Some(asm::Register::T3),
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rs2: Some(asm::Register::T2),
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});
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insts.push(asm::Instruction::IType {
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instr,
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rd,
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rs1: asm::Register::T3,
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rs1: asm::Register::T2,
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imm: asm::Immediate::Value(0),
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});
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}
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@@ -3204,8 +3253,8 @@ fn get_rhs_register(dtype: &ir::Dtype) -> asm::Register {
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fn get_res_register(dtype: &ir::Dtype) -> asm::Register {
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match dtype {
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ir::Dtype::Int { .. } | ir::Dtype::Pointer { .. } => asm::Register::T2,
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ir::Dtype::Float { .. } => asm::Register::FT2,
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ir::Dtype::Int { .. } | ir::Dtype::Pointer { .. } => asm::Register::T1,
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ir::Dtype::Float { .. } => asm::Register::FT1,
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_ => todo!(),
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}
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}
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Reference in New Issue
Block a user