Modify comments for cargo doc

src/asm/mod.rs

@@ -22,14 +22,16 @@ pub struct TranslationUnit {
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub struct Section<T> {
     /// Section Headers provice size, offset, type, alignment and flags of the sections
-    /// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#section-header
+    ///
+    /// For more details: <https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#section-header>
     pub header: Vec<Directive>,
     pub body: T,
 }
 
 /// An object file is made up of multiple sections, with each section corresponding to
 /// distinct types of executable code or data.
-/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#sections
+///
+/// For more details: <https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#sections>
 impl<T> Section<T> {
     pub fn new(header: Vec<Directive>, body: T) -> Self {
         Self { header, body }
@@ -76,7 +78,8 @@ impl Block {
 
 /// The assembler implements a number of directives that control the assembly of instructions
 /// into an object file.
-/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-directives
+///
+/// For more details: <https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-directives>
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub enum Directive {
     /// .align integer
@@ -129,7 +132,8 @@ pub enum SymbolType {
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub enum Instruction {
     /// R-type instruction format
-    /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p)
+    ///
+    /// For more details: <https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (104p)
     RType {
         instr: RType,
         rd: Register,
@@ -137,7 +141,8 @@ pub enum Instruction {
         rs2: Option<Register>,
     },
     /// I-type instruction format
-    /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p)
+    ///
+    /// For more details: <https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (104p)
     IType {
         instr: IType,
         rd: Register,
@@ -145,7 +150,8 @@ pub enum Instruction {
         imm: Immediate,
     },
     /// S-type instruction format
-    /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p)
+    ///
+    /// For more details: <https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (104p)
     SType {
         instr: SType,
         rs1: Register,
@@ -153,7 +159,8 @@ pub enum Instruction {
         imm: Immediate,
     },
     /// B-type instruction format
-    /// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (104p)
+    ///
+    /// For more details: <https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (104p)
     BType {
         instr: BType,
         rs1: Register,
@@ -506,8 +513,10 @@ pub enum UType {
 /// The assembler implements a number of convenience psuedo-instructions that are formed from
 /// instructions in the base ISA, but have implicit arguments or in some case reversed arguments,
 /// that result in distinct semantics.
-/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-pseudo-instructions
+///
-/// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (110p)
+/// For more details:
+/// - <https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#assembler-pseudo-instructions>
+/// - <https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (110p)
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub enum Pseudo {
     /// la rd, symbol
@@ -593,7 +602,8 @@ impl Immediate {
 
 /// The relocation function creates synthesize operand values that are resolved
 /// at program link time and are used as immediate parameters to specific instructions.
-/// https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
+///
+/// For more details: <https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md>
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub enum RelocationFunction {
     /// %hi
@@ -603,7 +613,8 @@ pub enum RelocationFunction {
 }
 
 /// `Label` is used as branch, unconditional jump targets and symbol offsets.
-/// https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#labels
+///
+/// For more details: <https://github.com/michaeljclark/michaeljclark.github.io/blob/master/asm.md#labels>
 #[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)]
 pub struct Label(pub String);
 
@@ -675,7 +686,8 @@ impl DataSize {
 
 // TODO: Add calling convention information (caller/callee-save registers)
 /// ABI name for RISC-V integer and floating-point register
-/// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf (109p)
+///
+/// For more details: <https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf> (109p)
 #[derive(Debug, Clone, PartialEq, Eq, Hash, Copy)]
 pub enum Register {
     Zero,

src/ir/interp.rs

@@ -26,7 +26,8 @@ pub enum Value {
         ///
         /// * Casting from an f32 to an f64 is perfect and lossless (f32 -> f64)
         /// * Casting from an f64 to an f32 will produce the closest possible value (f64 -> f32)
-        /// https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions
+        ///
+        /// For more details: <https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions>
         value: OrderedFloat<f64>,
         width: usize,
     },

src/ir/mod.rs

@@ -221,7 +221,8 @@ pub enum Instruction {
         target_dtype: Dtype,
     },
     /// `GetElementPtr` is inspired from `getelementptr` instruction of LLVM.
-    /// https://llvm.org/docs/LangRef.html#i-getelementptr
+    ///
+    /// For more details: <https://llvm.org/docs/LangRef.html#i-getelementptr>
     GetElementPtr {
         ptr: Operand,
         offset: Operand,
@@ -501,7 +502,8 @@ pub enum Constant {
         ///
         /// * Casting from an f32 to an f64 is perfect and lossless (f32 -> f64)
         /// * Casting from an f64 to an f32 will produce the closest possible value (f64 -> f32)
-        /// https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions
+        ///
+        /// For more details: <https://doc.rust-lang.org/stable/reference/expressions/operator-expr.html#type-cast-expressions>
         value: OrderedFloat<f64>,
         width: usize,
     },

src/lib.rs

@@ -44,7 +44,7 @@ mod tests;
 mod utils;
 mod write_base;
 
-mod asm;
+pub mod asm;
 mod c;
 pub mod ir;