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HW7 (5)

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static
2025-06-16 04:37:35 +00:00
parent 3232e30b46
commit 9ed3e7ca3f
1 changed files with 4 additions and 4 deletions
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8
src/asmgen/mod.rs
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@@ -57,7 +57,7 @@ impl Asmgen {
if *size != directives.len() { if *size != directives.len() {
directives.push(asm::Directive::Zero( directives.push(asm::Directive::Zero(
(size - directives.len()) (size - directives.len())
* (get_dtype_size(&inner, structs) as usize), * (get_dtype_size(inner, structs) as usize),
)); ));
} }
} }
@@ -610,7 +610,7 @@ impl Asmgen {
rid: ptr_rid, rid: ptr_rid,
dtype: ptr_dtype, dtype: ptr_dtype,
} => match ptr_rid { } => match ptr_rid {
ir::RegisterId::Temp { .. } => { ir::RegisterId::Temp { .. } | ir::RegisterId::Arg { .. } => {
if let Some(size) = is_struct(&value_dtype, structs) { if let Some(size) = is_struct(&value_dtype, structs) {
let rs1 = get_lhs_register(ptr_dtype); let rs1 = get_lhs_register(ptr_dtype);
self.translate_load_operand(ptr, rs1, context); self.translate_load_operand(ptr, rs1, context);
@@ -1058,7 +1058,7 @@ impl Asmgen {
rid: ptr_rid, rid: ptr_rid,
dtype: ptr_dtype, dtype: ptr_dtype,
} => match ptr_rid { } => match ptr_rid {
ir::RegisterId::Temp { .. } => { ir::RegisterId::Temp { .. } | ir::RegisterId::Arg { .. } => {
let rs1 = get_lhs_register(ptr_dtype); let rs1 = get_lhs_register(ptr_dtype);
let rs2 = get_rhs_register(&offset_dtype); let rs2 = get_rhs_register(&offset_dtype);
self.translate_load_operand(ptr, rs1, context); self.translate_load_operand(ptr, rs1, context);
@@ -1629,7 +1629,7 @@ fn ceil_to_multiple_of_16(x: u64) -> u64 {
fn get_dtype_size(dtype: &ir::Dtype, structs: &HashMap<String, Option<ir::Dtype>>) -> u64 { fn get_dtype_size(dtype: &ir::Dtype, structs: &HashMap<String, Option<ir::Dtype>>) -> u64 {
let (size, _) = dtype.size_align_of(structs).unwrap(); let (size, _) = dtype.size_align_of(structs).unwrap();
return size as u64; size as u64
} }
fn upgrade_dtype(dtype: &ir::Dtype) -> ir::Dtype { fn upgrade_dtype(dtype: &ir::Dtype) -> ir::Dtype {